Patent US5748527 - Nonvolatile memory having transistor redundancy - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA flash memory array comprises a primary row line and a redundant row line each having memory cells therealong. A method of accessing the flash memory array comprises preprogramming all said memory cells. Next, all memory cells are erased simultaneously. Subsequently, all memory cells along the primary...http://www.google.com/patents/US5748527?utm_source=gb-gplus-sharePatent US5748527 - Nonvolatile memory having transistor redundancyAdvanced Patent SearchPublication numberUS5748527 APublication typeGrantApplication numberUS 08/710,917Publication dateMay 5, 1998Filing dateSep 24, 1996Priority dateFeb 23, 1995Fee statusPaidAlso published asUS5559742Publication number08710917, 710917, US 5748527 A, US 5748527A, US-A-5748527, US5748527 A, US5748527AInventorsRoger R. Lee, Fernando GonzalezOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (26), Classifications (9), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNonvolatile memory having transistor redundancy
US 5748527 AAbstract
1. A method of programming a nonvolatile memory array, said memory array comprising at least primary and redundant conductive lines each having memory elements therealong, said method comprising the steps of:preprogramming all said memory elements along said primary and said redundant conductive lines; subsequent to said step of preprogramming, erasing all said memory elements along said primary and redundant conductive lines; and selecting a unique redundant signal path associated with said redundant conductive line to selectively program said memory elements along said redundant conductive line, wherein said memory elements along said primary conductive line are not read during any read cycle. 2. The method of claim 1 wherein said step of erasing all memory elements includes simultaneously erasing all said memory elements along said primary and redundant conductive lines.
6. A method of programming a nonvolatile memory array, said memory array comprising a plurality of primary row lines including a first primary row line, at least one redundant row line, and a plurality of column lines wherein each said primary row line has memory cells therealong, said method comprising the steps of:placing a first voltage on said first primary row line and on said plurality of column lines, and placing a second voltage lower than said first voltage on said plurality of row lines except said first primary row line, thereby programming all said memory cells along said first primary row line; subsequent to said step of programming all memory cells along said first primary row line, selectively programming said memory cells along said redundant row line, wherein said memory elements along said first primary row line are not read during any read cycle. 7. The method of claim 6 wherein threshold voltages of said memory cells along said redundant row line do not change substantially during said step of programming all memory cells along said first primary row line.
15. The method of claim 14 further comprising the steps of:applying a first potential to said redundant signal path associated with said redundant conductive line and a second potential to said redundant signal path associated with said primary conductive line; responsive to said application of said potentials to said redundant signal paths of said conductive lines, coupling said redundant conductive line with a first voltage signal and coupling said primary conductive line with a second voltage signal different from said first voltage signal. 16. The method of claim 15 wherein said step of coupling said conductive lines with said voltage signals includes a unique pass transistor associated with each said redundant signal path.
20. A method of programming a nonvolatile memory device comprising the following steps:providing a memory address; applying a first potential to a first redundancy signal path thereby coupling a first row line associated with said first redundancy signal path and with said address to a first voltage signal; and applying a second potential different from said first potential to a second redundancy signal path thereby coupling a second row line associated with said second redundancy signal path and with said address to a second voltage signal different from said first voltage signal. 21. The method of claim 20 further comprising the following steps:applying a third potential to a first primary signal path associated with said first row line while applying said first potential to said first redundancy signal path; applying said third voltage to a second primary signal path associated with said second row line while applying said second potential to said second redundancy signal path. 22. The method of claim 21 wherein said application of said first and second voltages includes a first unique pass transistor associated with said first redundancy signal path and a unique pass transistor associated with said second redundancy signal path.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5058071 *Jan 24, 1991Oct 15, 1991Mitsubishi Denki Kabushiki KaishaSemiconductor memory device having means for repairing the memory device with respect to possible defective memory portionsUS5157628 *Aug 10, 1990Oct 20, 1992Sony CorporationSemiconductor memoryUS5220518 *Oct 25, 1991Jun 15, 1993Vlsi Technology, Inc.Integrated circuit memory with non-binary array configurationUS5233559 *Feb 11, 1991Aug 3, 1993Intel CorporationRow redundancy for flash memoriesUS5329488 *Dec 3, 1992Jul 12, 1994Nec CorporationNonvolatile semiconductor memory device with redundancy circuitUS5388076 *Jul 2, 1993Feb 7, 1995Sharp Kabushiki KaishaSemiconductor memory device* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5949718 *Dec 17, 1997Sep 7, 1999Advanced Micro Devices, Inc.Method and system for selected source during read and programming of flash memoryUS6259309 *May 5, 1999Jul 10, 2001International Business Machines CorporationMethod and apparatus for the replacement of non-operational metal lines in DRAMSUS6335652Jan 18, 2001Jan 1, 2002International Business Machines CorporationMethod and apparatus for the replacement of non-operational metal lines in DRAMSUS6922366Apr 24, 2003Jul 26, 2005Stmicroelectronics S.R.L.Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory deviceUS6944072May 15, 2003Sep 13, 2005Stmicroelectronics S.R.L.Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory deviceUS7047455Sep 2, 2004May 16, 2006Micron Technology, Inc.Memory with element redundancyUS7076702Sep 2, 2004Jul 11, 2006Micron Technology, Inc.Memory with element redundancyUS7076703Nov 26, 2002Jul 11, 2006Advanced Micro Devices, Inc.Method and system for defining a redundancy window around a particular column in a memory arrayUS7162668Apr 19, 2001Jan 9, 2007Micron Technology, Inc.Memory with element redundancyUS7168013 *Sep 2, 2004Jan 23, 2007Micron Technology, Inc.Memory with element redundancyUS7437625Sep 2, 2004Oct 14, 2008Micron Technology, Inc.Memory with element redundancyUS7496811 *Feb 24, 2006Feb 24, 2009Kabushiki Kaisha ToshibaStorage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage mediumUS7551478 *Sep 14, 2006Jun 23, 2009Kabushiki Kaisha ToshibaApparatus, method and computer program product for reading information stored in storage mediumUS7640465Feb 22, 2007Dec 29, 2009Micron Technology, Inc.Memory with element redundancyUS8181131Apr 30, 2010May 15, 2012International Business Machines CorporationEnhanced analysis of array-based netlists via reparameterizationUS8281192Jan 16, 2009Oct 2, 2012Kabushiki Kaisha ToshibaStorage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage mediumUS8291359May 7, 2010Oct 16, 2012International Business Machines CorporationArray concatenation in an integrated circuit designUS8307313 *May 7, 2010Nov 6, 2012International Business Machines CorporationMinimizing memory array representations for enhanced synthesis and verificationUS8336016May 7, 2010Dec 18, 2012International Business Machines CorporationEliminating, coalescing, or bypassing ports in memory array representationsUS8478574Apr 30, 2010Jul 2, 2013International Business Machines CorporationTracking array data contents across three-valued read and write operationsUS8566764Apr 30, 2010Oct 22, 2013International Business Machines CorporationEnhanced analysis of array-based netlists via phase abstractionUS20110276930 *May 7, 2010Nov 10, 2011International Business Machines CorporationMinimizing Memory Array Representations for Enhanced Synthesis and VerificationCN100477012CJul 10, 2003Apr 8, 2009斯班逊有限公司Method and system for defining a redundancy window around a particular column of a memory arrayEP1365419A1 *May 21, 2002Nov 26, 2003STMicroelectronics S.r.l.Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device thereforEP1403879A1 *Sep 30, 2002Mar 31, 2004STMicroelectronics S.r.l.Method for replacing failed non-volatile memory cells and corresponding memory deviceWO2004049350A1 *Jul 10, 2003Jun 10, 2004Advanced Micro Devices IncMethod and system for defining a redundancy window around a particular column in a memory array* Cited by examinerClassifications U.S. Classification365/185.09, 365/200, 365/185.33International ClassificationG11C16/16, G11C29/00Cooperative ClassificationG11C29/82, G11C16/16European ClassificationG11C29/82, G11C16/16Legal EventsDateCodeEventDescriptionOct 7, 2009FPAYFee paymentYear of fee payment: 12Oct 14, 2005FPAYFee paymentYear of fee payment: 8Sep 27, 2001FPAYFee paymentYear of fee payment: 4Jan 5, 1999CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services
Patent US5748527 - Nonvolatile memory having transistor redundancy - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA flash memory array comprises a primary row line and a redundant row line each having memory cells therealong. A method of accessing the flash memory array comprises preprogramming all said memory cells. Next, all memory cells are erased simultaneously. Subsequently, all memory cells along the primary...http://www.google.com/patents/US5748527?utm_source=gb-gplus-sharePatent US5748527 - Nonvolatile memory having transistor redundancyAdvanced Patent SearchPublication numberUS5748527 APublication typeGrantApplication numberUS 08/710,917Publication dateMay 5, 1998Filing dateSep 24, 1996Priority dateFeb 23, 1995Fee statusPaidAlso published asUS5559742Publication number08710917, 710917, US 5748527 A, US 5748527A, US-A-5748527, US5748527 A, US5748527AInventorsRoger R. Lee, Fernando GonzalezOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (26), Classifications (9), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetNonvolatile memory having transistor redundancy
US 5748527 AAbstract
1. A method of programming a nonvolatile memory array, said memory array comprising at least primary and redundant conductive lines each having memory elements therealong, said method comprising the steps of:preprogramming all said memory elements along said primary and said redundant conductive lines; subsequent to said step of preprogramming, erasing all said memory elements along said primary and redundant conductive lines; and selecting a unique redundant signal path associated with said redundant conductive line to selectively program said memory elements along said redundant conductive line, wherein said memory elements along said primary conductive line are not read during any read cycle. 2. The method of claim 1 wherein said step of erasing all memory elements includes simultaneously erasing all said memory elements along said primary and redundant conductive lines.
6. A method of programming a nonvolatile memory array, said memory array comprising a plurality of primary row lines including a first primary row line, at least one redundant row line, and a plurality of column lines wherein each said primary row line has memory cells therealong, said method comprising the steps of:placing a first voltage on said first primary row line and on said plurality of column lines, and placing a second voltage lower than said first voltage on said plurality of row lines except said first primary row line, thereby programming all said memory cells along said first primary row line; subsequent to said step of programming all memory cells along said first primary row line, selectively programming said memory cells along said redundant row line, wherein said memory elements along said first primary row line are not read during any read cycle. 7. The method of claim 6 wherein threshold voltages of said memory cells along said redundant row line do not change substantially during said step of programming all memory cells along said first primary row line.
15. The method of claim 14 further comprising the steps of:applying a first potential to said redundant signal path associated with said redundant conductive line and a second potential to said redundant signal path associated with said primary conductive line; responsive to said application of said potentials to said redundant signal paths of said conductive lines, coupling said redundant conductive line with a first voltage signal and coupling said primary conductive line with a second voltage signal different from said first voltage signal. 16. The method of claim 15 wherein said step of coupling said conductive lines with said voltage signals includes a unique pass transistor associated with each said redundant signal path.
20. A method of programming a nonvolatile memory device comprising the following steps:providing a memory address; applying a first potential to a first redundancy signal path thereby coupling a first row line associated with said first redundancy signal path and with said address to a first voltage signal; and applying a second potential different from said first potential to a second redundancy signal path thereby coupling a second row line associated with said second redundancy signal path and with said address to a second voltage signal different from said first voltage signal. 21. The method of claim 20 further comprising the following steps:applying a third potential to a first primary signal path associated with said first row line while applying said first potential to said first redundancy signal path; applying said third voltage to a second primary signal path associated with said second row line while applying said second potential to said second redundancy signal path. 22. The method of claim 21 wherein said application of said first and second voltages includes a first unique pass transistor associated with said first redundancy signal path and a unique pass transistor associat
ed with said second redundancy signal path.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5058071 *Jan 24, 1991Oct 15, 1991Mitsubishi Denki Kabushiki KaishaSemiconductor memory device having means for repairing the memory device with respect to possible defective memory portionsUS5157628 *Aug 10, 1990Oct 20, 1992Sony CorporationSemiconductor memoryUS5220518 *Oct 25, 1991Jun 15, 1993Vlsi Technology, Inc.Integrated circuit memory with non-binary array configurationUS5233559 *Feb 11, 1991Aug 3, 1993Intel CorporationRow redundancy for flash memoriesUS5329488 *Dec 3, 1992Jul 12, 1994Nec CorporationNonvolatile semiconductor memory device with redundancy circuitUS5388076 *Jul 2, 1993Feb 7, 1995Sharp Kabushiki KaishaSemiconductor memory device* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5949718 *Dec 17, 1997Sep 7, 1999Advanced Micro Devices, Inc.Method and system for selected source during read and programming of flash memoryUS6259309 *May 5, 1999Jul 10, 2001International Business Machines CorporationMethod and apparatus for the replacement of non-operational metal lines in DRAMSUS6335652Jan 18, 2001Jan 1, 2002International Business Machines CorporationMethod and apparatus for the replacement of non-operational metal lines in DRAMSUS6922366Apr 24, 2003Jul 26, 2005Stmicroelectronics S.R.L.Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory deviceUS6944072May 15, 2003Sep 13, 2005Stmicroelectronics S.R.L.Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory deviceUS7047455Sep 2, 2004May 16, 2006Micron Technology, Inc.Memory with element redundancyUS7076702Sep 2, 2004Jul 11, 2006Micron Technology, Inc.Memory with element redundancyUS7076703Nov 26, 2002Jul 11, 2006Advanced Micro Devices, Inc.Method and system for defining a redundancy window around a particular column in a memory arrayUS7162668Apr 19, 2001Jan 9, 2007Micron Technology, Inc.Memory with element redundancyUS7168013 *Sep 2, 2004Jan 23, 2007Micron Technology, Inc.Memory with element redundancyUS7437625Sep 2, 2004Oct 14, 2008Micron Technology, Inc.Memory with element redundancyUS7496811 *Feb 24, 2006Feb 24, 2009Kabushiki Kaisha ToshibaStorage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage mediumUS7551478 *Sep 14, 2006Jun 23, 2009Kabushiki Kaisha ToshibaApparatus, method and computer program product for reading information stored in storage mediumUS7640465Feb 22, 2007Dec 29, 2009Micron Technology, Inc.Memory with element redundancyUS8181131Apr 30, 2010May 15, 2012International Business Machines CorporationEnhanced analysis of array-based netlists via reparameterizationUS8281192Jan 16, 2009Oct 2, 2012Kabushiki Kaisha ToshibaStorage medium reproducing apparatus, storage medium reproducing method, and computer program product for reading information from storage mediumUS8291359May 7, 2010Oct 16, 2012International Business Machines CorporationArray concatenation in an integrated circuit designUS8307313 *May 7, 2010Nov 6, 2012International Business Machines CorporationMinimizing memory array representations for enhanced synthesis and verificationUS8336016May 7, 2010Dec 18, 2012International Business Machines CorporationEliminating, coalescing, or bypassing ports in memory array representationsUS8478574Apr 30, 2010Jul 2, 2013International Business Machines CorporationTracking array data contents across three-valued read and write operationsUS8566764Apr 30, 2010Oct 22, 2013International Business Machines CorporationEnhanced analysis of array-based netlists via phase abstractionUS20110276930 *May 7, 2010Nov 10, 2011International Business Machines CorporationMinimizing Memory Array Representations for Enhanced Synthesis and VerificationCN100477012CJul 10, 2003Apr 8, 2009斯班逊有限公司Method and system for defining a redundancy window around a particular column of a memory arrayEP1365419A1 *May 21, 2002Nov 26, 2003STMicroelectronics S.r.l.Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device thereforEP1403879A1 *Sep 30, 2002Mar 31, 2004STMicroelectronics S.r.l.Method for replacing failed non-volatile memory cells and corresponding memory deviceWO2004049350A1 *Jul 10, 2003Jun 10, 2004Advanced Micro Devices IncMethod and system for defining a redundancy window around a particular column in a memory array* Cited by examinerClassifications U.S. Classification365/185.09, 365/200, 365/185.33International ClassificationG11C16/16, G11C29/00Cooperative ClassificationG11C29/82, G11C16/16European ClassificationG11C29/82, G11C16/16Legal EventsDateCodeEventDescriptionOct 7, 2009FPAYFee paymentYear of fee payment: 12Oct 14, 2005FPAYFee paymentYear of fee payment: 8Sep 27, 2001FPAYFee paymentYear of fee payment: 4Jan 5, 1999CCCertificate of correctionRotateOriginal ImageGoogle Home - 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